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Analog And Digital Electronics

Semester :  III

Course Code : 18CS33

CIE Marks : 40                    SEE Marks : 60

(18CS33 )



Photodiodes, Light Emitting Diodes and Optocouplers, BJT Biasing: Fixed bias, Collector to base Bias, voltage divider bias, Operational Amplifier Application Circuits: Multivibrators using IC-555, Peak Detector, Schmitt trigger, Active Filters, Non-Linear Amplifier, Relaxation Oscillator, Current-to-Voltage and Voltage-to-Current Converter, Regulated Power Supply Parameters, adjustable voltage regulator, D to A and A to D converter.
Text Book 1 :Part A:Chapter 2(Section 2.9,2.10,2.11), Chapter 4(Section 4.2 ,4.3,4.4),Chapter 7 (section (7.2,7.3.1,7.4,7.6 to 7.11), Chapter 8 (section (8.1,8.5), Chapter 9


Karnaugh maps: minimum forms of switching functions, two and three variable Karnaugh maps, four variable karnaugh maps, determination of minimum expressions using essential prime implicants, Quine-McClusky Method: determination of prime implicants, The prime implicant chart, petricks method, simplification of incompletely specified functions, simplification using map-entered variables
Textbook 1:Part B: Chapter 5 ( Sections 5.1 to 5.4) Chapter 6(Sections 6.1 to 6.5)


Combinational circuit design and simulation using gates: Review of Combinational circuit design, design of circuits with limited Gate Fan-in, Gate delays and Timing diagrams, Hazards in combinational Logic, simulation and testing of logic circuits
Multiplexers, Decoders and Programmable Logic Devices: Multiplexers, three-state buffers, decoders and encoders, Programmable Logic devices, Programmable Logic Arrays, Programmable Array Logic.
Textbook 1:Part B: Chapter 8, Chapter 9 (Sections 9.1 to 9.6)


Introduction to VHDL: VHDL description of combinational circuits, VHDL Models for multiplexers, VHDL Modules.
Latches and Flip-Flops: Set Reset Latch, Gated Latches, Edge-Triggered D Flip Flop 3, SR Flip Flop, J K Flip Flop, T Flip Flop, Flip Flop with additional inputs, Asynchronous Sequential Circuits
Textbook 1:Part B: Chapter 10(Sections 10.1 to 10.3), Chapter 11 (Sections 11.1 to 11.9) 


Registers and Counters: Registers and Register Transfers, Parallel Adder with accumulator, shift registers, design of Binary counters, counters for other sequences, counter design using SR and J K Flip Flops, sequential parity checker, state tables and graphs
Text book 1:Part B: Chapter 12(Sections 12.1 to 12.5),Chapter 13(Sections 13.1,13.3

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