Digital System Design using Verilog (DSD) VTU Notes - BEC302
| VTU NOTES | |
|---|---|
|
Subject code |
BEC302 |
|
Semester |
3rd |
Module - 1
Principles of Combinational Logic: Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps-up to 4 variables, QuineMcCluskey Minimization Technique. Quine-McCluskey using Don’t CareTerms.(
Module - 2
Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices(PLDs)
Module - 3
Flip-Flops and its Applications: The Master-Slave Flip-flops(Pulse-Triggered flip-flops):SR flipflops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using clocked T, J K, D and SR flip-flops.
Module - 4
Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles ofDescription. (Section1.1to1.6.2, 1.6.4 (only Verilog),2 of Text 3)
Verilog Data flow description: Highlights of Data flow description, Structure of Data flowdescription.(Section2.1to2.2(only Verilog) of Text3)
Module - 5
Verilog Behavioral description: Structure, Variable Assignment Statement, SequentialStatements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1).(Section 3.1 to 3.4 (onlyVerilog)of Text 3)
Verilog Structural description: Highlights of Structural description, Organization of structural description, Structural description of ripple carry adder.(Section4.1 to 4.2 of Text 3)