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digital system design using verilog

Semester : VI

Course Code : 18EC644

CIE Marks : 40                       SEE Marks : 60

digital system design using verilog



Introduction and Methodology: Digital Systems and Embedded Systems, Real-World Circuits, Models, Design Methodology (1.1, 1.3 to 1.5 of Text). 
Combinational Basics: Combinational Components and Circuits, Verificationof Combinational Circuits (2.3 and 2.4 of Text). Number Basics: Unsigned integers, Signed Integers, Fixed point Numbers, Floating-point Numbers (3.1.1, 3.2.1, 3.3.1 and 3.4).
Sequential Basics: Sequential Datapaths and Control Clocked SynchronousTiming Methodology(4.3 up to 4.3.1, 4.4 up to 4.4.1 of Text). L1, L2, L3


Memories: Concepts, Memory Types, Error Detection and Correction (Chap 5 of Text). L1, L2, L3


Implementation Fabrics: Integrated Circuits, Programmable Logic Devices, Packaging and Circuit boards, Interconnection and Signal integrity (Chap 6 of Text). L1, L2, L3


I/O interfacing: I/O devices, I/O controllers, Parallel Buses, Serial Transmission, I/O software (Chap 8 of Text). L1, L2, L3


Design Methodology: Design flow, Design optimization, Design for the test, Nontechnical Issues (Chap 10 of Text). L1, L2, L3, L4